This invention relates generally to bipolar monolithic integrated circuit read only memory (ROM) and programmable read only memory (PROM) components are more particularly to standby power enable circuitry used in such ROM/PROM components and programming enable circuitry used in such PROM components.
As is known in the art, bipolar monolithic integrated circuit ROM/PROM components are widely used for storage of program and microprogram control instructions because such components are relatively fast and nonvolatile, retaining such instructions even when supply power is removed. Such bipolar monolithic integrated circuit ROM/PROM components generally include a memory element array coupled to addressing and output circuitry. Such addressing circuitry includes N-P-N output transistors, each having an emitter electrode connected to a ground bus, a collector electrode coupled to a +V.sub.cc bus and a base electrode coupled to a control signal for switching such transistor between an "on" or saturation state and an "off" state selectively in accordance with the control signal. In order to reduce the amount of power consumed by the addressing circuitry when such component is not selected standby power enable circuitry is included in the component. However, even when such component is in a standby condition such standby circuitry has heretofore resulted in an undesirable amount of power consumption, typically in the order of 500 milliwatts per component. One such standby power enable circuit includes the use of a P-N-P switching transistor having its emitter electrode coupled to the positive terminal (V.sub.cc ') of a power supply, its base electrode coupled to an enable signal source and also coupled to the V.sub.cc ' power supply terminal through a resistor and its collector electrode coupled to the +V.sub.cc bus of the component. In order to minimize the ROM/PROM access time it is desirable that the P-N-P switching transistor be a high speed device. One class of high current/high speed transistors is a transistor having a Schottky-barrier diode clamp formed between the base and collector regions of such transistor. Such Schottky-barrier diode clamp may be readily formed in a monolithic integrated circuit with N-P-N transistors by forming a platinum silicide layer under the base region metal contact which extends under such contact from a portion of the base region of a P type conductivity to an adjacent portion of the collector region of N type conductivity material. The interaction of the platinum and the N type silicon forms a diode between the base and collector regions of the transistor. Such fabrication technique, however, is not available in the formation of P-N-P Schottky barrier diode transistors.
A second standby power enable circuit includes the use of an N-P-N emitter follower transistor having a pullup resistor coupled between the base electrode of such transistor and the positive terminal, V.sub.cc ', of the power supply. The emitter electrode of such N-P-N transistor is coupled to the +V.sub.cc bus and the collector electrode is coupled to the positive terminal V.sub.cc ' of the power supply. The N-P-N transistor is "off" (i.e. the component therefor disabled) when a "low" signal is supplied to the base electrode of the N-P-N transistor. Here, however, power dissipation occurs in the pullup resistor when the component is in the standby condition. Further, while it is desirable to minimize the resistance of the pullup resistor in order to minimize the V.sub.CE drop between V.sub.cc ' and +V.sub.cc when the component is enabled, reducing the resistance of the pullup resistor increases the power consumption in such pullup resistor when the component is in the disable condition.